In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called metallization, and is performed using a number of different photolithographic and deposition techniques.
One metallization process, which is called the "damascene" technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer may be deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer to prevent diffusion of subsequently deposited conductive material into the oxide layer and the semiconductor devices (the combination of adhesion and barrier material is collectively referred to as "barrier layer" herein). It should be noted that some barrier materials also have good adhesion which is why the adhesion layer is optional. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metallization process, which is called the "dual damascene" technique is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride layer over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride layer. This is followed by deposition of a thin via nitride layer. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride layer. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride layer and the exposed oxide in the via area of the via nitride layer. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), or titanium nitride (TiN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as titanium, is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited barrier layers to underlying doped regions and/or conductive channels. The barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride (Ti/TiN) have been found to be useful as adhesion/barrier material combination for copper interconnects.
The "barrier effectiveness" of a barrier layer with respect to a conductive material is its ability to prevent diffusion of the conductive material. The barrier effectiveness of a barrier layer is determined in part by its thickness, including the thickness uniformity, and its quality, including the number and sizes of defects such as pinholes which form on deposition. To resist copper diffusion, it is found that a minimum barrier layer thickness of 5 nm is required. However, to minimize the electrical resistance due to the barrier layer, it is desirable to maintain a thin barrier layer. Therefore, it is desirable to keep the barrier layer thickness close to about 5 nm.
Barrier layers for copper interconnect in a damascene process are typically deposited by physical vapor deposition (PVD) or derivatives of PVD techniques. The common problems associated with most of these deposition techniques are poor sidewall step coverage and conformality, i.e., the barrier layer thickness is much higher in wide-open areas, such as on top of the channel oxide layer and in the upper portion of the sidewalls of the channels and vias than in the lower portion of the sidewalls of the channels and vias. To guarantee a minimum barrier layer thickness of 5 nm anywhere in the channel or via openings, including at the lower portion of the sidewalls, the barrier layer thickness in wide-open areas tends to be much higher than 5 nm. This increase in barrier layer thickness in the wide-open areas undesirably increases the electrical resistance of the barrier layer. Further, as the width of the channels and vias have decreased in size due to the size reduction in the semiconductor devices, an excessively thick barrier layer in the wide-open areas interferes with the subsequent filling of the channel and via openings with conductive materials.
A solution, which would form barrier layers in channel or via openings and result in a reduction in the electrical resistance of the barrier layers without a decrease in its barrier effectiveness and an improvement in the subsequent filling of the channel or via openings by conductive materials, has long been sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and diffusiveness through dielectrics, it is becoming more pressing that a solution be found.